1. Field of the Invention
The present invention relates to a divider, particularly to a floating point divider carrying out division of floating point data whose base is 16 (hereinafter to be called hexadecimal division).
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of one example of a conventional divider which carries out hexadecimal division. In addition, FIG. 1 is a block diagram of a divider shown in the FIG. 1 of Japanese Patent Application Laid-Open No. 1-125625 (1988).
In the conventional divider, at first, a mantissa of a dividend being floating point data whose base is 16 is inputted from the outside through a signal line 170 and set in a register 151. The upper three bits set in the register 151 are sent to an encoder 152 through a signal line 171, and the number of leading zero is detected there, the number of leading zero is held in a register 153 through a signal line 172. The number of leading zero is also sent to a shifter 158 as a shift number by the fact that a selector 156 selects the signal line 172 corresponding to a signal outputted by a control circuit 160 to a signal line 180.
On the other land, by the fact that a selector 157 selects an input line 176 corresponding to a signal outputted by the control circuit 160 to a signal line 183, and the control circuit 160 outputs a signal to a signal line 181 to direct the shifter 158 to shift to the left direction, the shifter 158 shifts the output (a mantissa of a dividend) of the register 151 to the left by the number of leading zero. A dividend which has been normalized such a way with the base being 2 (hereinafter to be called binary normalization) is held in a dividend register (not shown) inside of a convergence binary dividing circuit 159.
Next, the mantissa of divisor being floating point data whose base is 16 is inputted from the outside through a signal line 170 and set in the register 151. In case of a divisor, the same operation as the case of a dividend is performed except that the number of leading zero is held in a register 154 and that a divisor which has been binary-normalized is held in a divisor register (not shown) inside of the convergence binary dividing circuit 159. Thereafter, by a direction given from the control circuit 160 through a signal line 182, the convergence binary dividing circuit 159 performs a convergence division with the base being 2.
The result of division is outputted in the binary-normalized data from the convergence binary dividing circuit 159 to a signal line 179, however, the bits thereof have been shifted by the left shifting performed at binary normalizing of the division and the dividend. And since the radix point is shifted by the convergence division from the position at which the base is 16, a compensation shift is required. The compensation shift quantity therefor can be obtained by calculating the output of the register 153 and the output of the register 154 at an arithmetic circuit 155. As a result of this operation, when a carry out (signal line 175) becomes "0", by the fact that the selector 156 selects a signal line 173 corresponding to a signal outputted to the signal line 180 by the control circuit 160, the output of the arithmetic circuit 155 is sent to the shifter 158 through a signal line 174, and further a selector 157 selects the signal line 179 corresponding to a signal outputted to the signal line 183 by the control circuit 160. Thereby, the division result of the output of the dividing circuit 159 is outputted after the mantissa and exponent of the division result is compensated by the shifter 158 on the basis of the compensation shift quantity calculated by the arithmetic circuit 155 to be normalized with the base being 16 (hereinafter to be called hexadecimal normalization), from the shifter 158 as output data.
In the aforesaid conventional example, a convergence division method is used as a division algorithm, however, when other algorithm such as a restoring method or a non restoring method is used, mantissa data of a divisor and a dividend is binary-normalized before division, shift quantity at binary normalizing is held, mantissa data of division result is hexadecimal-normalized after executing division, and an exponent is calculated from the shift quantity at hexadecimal-normalizing and the binary-normalizing shift quantity which has been held, in the same way as the convergence division method, thereby to obtain a division result.
In the aforesaid conventional divider which performs hexadecimal division, since mantissa data of a divisor and dividend with the base being 16 is binary-normalized and is divided after that, and after executing division, the division result outputted in the binary-normalized form is hexadecimal-normalized, not only a medium called a binary normalization shift is required but means for compensating bit shift caused at binary normalizing shift as well, therefore there are problems that the processings are complicated and the operation takes a lot of time. There also is a problem that the number of hardwares is increased since whole bits of mantissa data must be shifted to perform binary-normalizing shift a register for holding the binary-normalizing shift quantity and hexadecimal-normalizing shift quantity must be provided in order to compensate bit shift of the division result to obtain a proper exponent data.